AI 基礎設施
AMD Helios Brings 72 MI455X GPUs Into a Single Memory Domain, Delivering 31 TB of HBM4 per Rack
AMD has officially unveiled the CDNA 5-based Instinct MI455X and the 72-accelerator Helios rack. The new platform challenges NVIDIA NVL72 with open interconnects and greater HBM capacity, although the performance figures disclosed so far are still primarily theoretical peaks.
At Advancing AI 2026, AMD officially unveiled the Instinct MI455X and provided the remaining hardware details for the Helios rack. Each MI455X uses the CDNA 5 architecture and consists of 2 nm compute dies, 3 nm I/O and cache dies, and 12 HBM4 stacks, containing 320 billion transistors in total. Each GPU is equipped with 432 GB of HBM4 and 23.3 TB/s of memory bandwidth, with theoretical peak performance of 40.3 PFLOPS in OCP MXFP4 or approximately 5 PFLOPS in BF16.
Helios integrates 72 MI455X GPUs, 18 EPYC Venice CPUs, Pensando networking, and the ROCm software stack into a double-wide rack. The complete rack provides approximately 31.1 TB of HBM4, 1.7 PB/s of memory bandwidth, and 2.9 EFLOPS of MXFP4 performance. The GPUs are connected via UALink-over-Ethernet to form a single coherent scale-up domain, while Ultra Ethernet is used between racks. The system follows the Open Compute Project’s Open Rack Wide mechanical specification, allowing cloud providers to modify the reference design according to their power, cooling, and networking requirements instead of being limited to a fixed configuration.
The key technical advantage is not just FLOPS, but the combination of 432 GB of memory per accelerator and a coherent 72-GPU domain. For large-scale mixture-of-experts (MoE) inference, more model weights and KV cache data can remain in HBM, reducing cross-rack transfers. Each GPU’s 2.4 Tb/s scale-out bandwidth also targets large-scale expert parallelism. On the other hand, the 256 GB/s Infinity Fabric connection between Venice and the GPUs is significantly slower than NVIDIA Vera–Rubin’s host interconnect, and storage data must also pass through the CPU path, potentially limiting data-intensive training workloads.
AMD directly compares the theoretical peaks of different low-precision formats with NVIDIA Rubin, but MXFP4 and NVFP4 do not use exactly the same scaling and sparsity definitions, so these figures cannot be used to infer real-world token throughput. Engineering teams should next evaluate ROCm kernel maturity, end-to-end benchmarks for mainstream models, power consumption and liquid-cooling requirements, and whether different customized Helios configurations can maintain the claimed communication efficiency.