ACE-RTL Has Nemotron Iteratively Compile and Fix Verilog, Achieving a 97.1% Average Pass Rate Across Nine Task Categories

NVIDIA has published its latest RTL programming results for the combination of Nemotron 3 Ultra and ACE-RTL: an average pass rate of 97.1% across nine categories of agentic tasks in Comprehensive Verilog Design Problems (CVDP). According to NVIDIA’s comparison, this configuration outperformed models including GLM 5.2 and Kimi K2.6 while using up to 71% fewer tokens per iteration. This is not a text-based benchmark in which Verilog is generated in a single pass. Instead, the agent reads a project, generates or modifies RTL, runs compilation and tests, and then makes corrections based on error messages.

At the core of ACE-RTL is an iterative generate-test-reflect loop. The agent first analyzes the specification and existing files, writes a candidate implementation, and then invokes a simulator or verification tool to obtain executable feedback. Errors, test results, and previous attempts are organized into an evolving context. This approach turns the formal constraints of HDL into something resembling an automated evaluator, so the model does not have to rely solely on language probabilities to guess whether the syntax, timing, and interfaces are correct. Nemotron 3 Ultra itself is a hybrid Mamba-Attention MoE with 550B total parameters and 55B active parameters. Its long context window also helps preserve specifications, module dependencies, and multi-round verification records.

The public CVDP repository contains 783 human-authored problems spanning 13 categories, including RTL generation, debugging, specification-to-code translation, assertions, verification, and question answering. The reported 97.1% applies only to nine categories involving agentic workflows and should not be interpreted as evidence that the model can design and sign off an entire chip. Benchmark tasks typically have explicit tests and bounded project scopes, whereas real-world EDA workflows also involve incomplete specifications, PPA trade-offs, clock-domain crossings, third-party IP, and expensive simulations.

Engineering teams should next examine the sample count for each task category, retry limits, tool versions, and failure distributions instead of relying only on the average pass rate. Because ACE-RTL-related data has also been used to train Nemotron, evaluation decontamination and the similarity of benchmark problems are especially important. Only if third parties can reproduce the results on the public CVDP benchmark under a fixed token budget and with the same simulator can agents with executable feedback potentially become a trusted support layer for RTL review and verification.