AI 基礎設施
SiFive and AMD Demo ROCm 10 Running on a RISC-V Host, Offloading Gemma Inference to a Radeon GPU
SiFive booted ROCm 10 on a BigSky server powered by a P870-D RISC-V CPU, with a Radeon AI PRO R9700 running Gemma4-E2B inference. The demo shows that non-x86, non-Arm hosts can connect to AMD’s GPU software stack, although no performance data, reproducible image, or formal support scope has yet been released.
SiFive and AMD demonstrated a heterogeneous AI inference system at the AI Infra Summit. A BigSky SF-2U870 server uses 32 SiFive P870-D RISC-V cores running at 2.0 GHz as the host, connects to an AMD Radeon AI PRO R9700 GPU over PCIe, and runs Gemma4-E2B on ROCm 10.0. The GPU handles model computation, while the RISC-V CPU is responsible for the operating system, runtime, data preparation, and inference orchestration. The key point, therefore, is not that the RISC-V cores compute the Transformer directly, but that ROCm’s host-side components can operate on a different ISA.
The technical significance of the demonstration is that AI accelerator software typically includes far more than GPU kernels. The HIP runtime, driver interfaces, memory management, PyTorch or inference-framework dependencies, and container and monitoring tools may all contain implicit x86-64 or Arm64 assumptions. If ROCm can load models, transfer tensors, and launch kernels from a RISC-V server, hardware designers could combine an open-instruction-set control plane with AMD GPUs without also tying the host CPU to an established platform.
BigSky itself is a development platform for porting, tuning, and validation, rather than a production AI cluster built specifically for this demonstration. The SF-2U870 includes 256GB of DDR5-5600 memory, four PCIe 5.0 x16 slots, two 7.68TB U.2 NVMe drives, and 10/25Gb networking. Its ample PCIe connectivity makes it suitable for testing multiple accelerator cards, but the announcement mentions only the R9700 and Gemma4-E2B. It provides no details about model precision, batch size, context length, time to first token, token throughput, or power consumption, and it does not publish build scripts or container hashes.
The demonstration should therefore still be viewed as a compatibility milestone showing that the software stack can run end to end, rather than proof that RISC-V can already replace mature AI host platforms on performance. Engineers should next watch whether upstream ROCm adds riscv64 packages and CI, whether higher-level frameworks such as PyTorch and vLLM can be installed natively, and whether IOMMU and pinned memory are stable, as well as the state of multi-GPU operation, RCCL, fault telemetry, and the formal support matrix. Only when these components are reproducible and maintained over the long term will the demonstration translate into a deployable data-center option.