影片生成／推論系統
NVIDIA Adds Two-Stage Generation for MiniMax H3, Cutting 10-Second Video Latency to 14.9 Seconds on a Single GB200
H3 Super Acceleration first creates a low-resolution draft with four denoising steps, then uses LTX and Sol-Attn to complete high-resolution refinement in three steps. NVIDIA reports that 768p, 10-second video generation is 27.7× faster than the SGLang baseline, but the acceleration changes the sampling path and is not a pure kernel optimization at equivalent quality.
NVIDIA's SANA team has updated H3 Super Acceleration, its inference approach for MiniMax H3. Rather than proportionally accelerating every compute kernel in the original model, the approach repartitions the generation workload. In the first stage, H3, a dedicated LoRA, and a lightweight decoder run four denoising steps at 896×512 and 24 FPS. In the second stage, the draft is upscaled to 768p, 1080p, or 2K, after which the LTX model and Sol-Attn perform three refinement steps followed by fast VAE decoding. The two stages run sequentially on a single GB200, for a total of seven steps.
In warmed-up tests at 1344×768 with a batch size of 1, a five-second video took 6.852 seconds and a ten-second video took 14.931 seconds. NVIDIA lists the corresponding SGLang baselines as 152.3 and 414.1 seconds, translating to speedups of 22.2× and 27.7×, respectively. A further breakdown shows that TAEH3 reduced first-stage VAE decoding time from 3.427 seconds to 0.028 seconds, while LTX TAEHV cut final decoding time from 6.404 seconds to 0.187 seconds. The engineering takeaway is that the main source of latency in video services is not necessarily limited to the DiT: decoders, resolution scheduling, and refinement models can also dominate end-to-end cost.
These figures still should not be treated as lossless kernel acceleration. The new pipeline reduces the number of full-resolution H3 steps and uses a different model to restore detail, so textures, motion, and audio may all diverge from the original SGLang output. The measurements also exclude model loading and warm-up, and the second-stage result is only an average of ten warm requests. NVIDIA has not yet disclosed concurrency performance, tail latency, peak VRAM usage, or objective quality metrics. The next questions are whether the code and LoRA weights will be released in full, whether consumer GPUs can accommodate both models, and whether the same speed and visual quality can be sustained in high-throughput serving.