MicroEvo Uses LLMs and MCTS for Processor Design, Requiring 10.6× Fewer Simulations Than NSGA-II to Reach the Target

A team from Southeast University, NVIDIA, and other institutions has introduced MicroEvo, which applies large language models to multi-objective design-space exploration for processor microarchitectures. Such work must simultaneously reduce CPI, power consumption, and area, while parameters including register counts, issue width, caches, and branch predictors constrain one another. Testing each candidate configuration therefore requires costly cycle-accurate simulation and power modeling.

MicroEvo uses Monte Carlo Tree Search to manage candidate designs. Pareto-UCT jointly considers a candidate configuration’s contribution to hypervolume, its coverage of the objective space, and the degree to which it remains unexplored. The LLM performs either local modifications or larger structural mutations within valid discrete parameter ranges. The system also compares the PPA results of parent and child designs, summarizing which combinations work as retrievable natural-language memories. If no significant improvement occurs over multiple rounds, a state controller changes the prompt strategy from exploit to balance or explore, helping the search avoid remaining trapped at a local optimum.

The main experiment began with five initial samples and ran for 10 rounds, totaling 45 simulations. RISC-V cores were evaluated using gem5 and McPAT, with all results averaged across five independent trials. The Gemini-3-pro version achieved 23.94% higher hypervolume than NSGA-II, with a maximum relative gain of 36.22% in one specific design space. Given a target HV threshold of 0.74, it required 10.6× fewer evaluations, while the time needed to reach the target was only 8.3% of Boom-Explorer’s. The team also tested scalability on the more complex XiangShan Kunminghu core using XS-GEM5.

The MIT-licensed repository provides the search core, Alpha, BOOM, and XiangShan design spaces, as well as gem5-to-McPAT integration. Users must still compile the simulators, McPAT, and benchmark programs themselves. Notably, the reference Pareto set was constructed by combining 5,000 random points with the solutions found by all evaluated methods, and the 10.6× figure also depends on the selected HV threshold. The next step should be to validate candidate designs through RTL synthesis, timing analysis, and ultimately post-silicon measurements, while testing whether different models and prompts can consistently reproduce the search advantage.