MicroEvo Uses LLMs and MCTS to Search Processor Designs, Improving Pareto Quality by Up to 36.2%

Researchers from Southeast University, NVIDIA, and other institutions have introduced MicroEvo, which places a large language model inside a multi-objective search loop for processor microarchitectures. Such design spaces involve parameters including fetch width, reorder buffer size, issue queues, caches, and branch predictors. With just 22 categories of settings, the paper’s baseline core yields approximately 3.95×10¹³ combinations; when expanded to the XiangShan Kunminghu core, the space grows to approximately 3.41×10²⁶ combinations. Each candidate must also undergo cycle-accurate simulation and power and area estimation. The key, therefore, is not exhaustive enumeration but directing a limited evaluation budget toward regions more likely to improve performance, power, and area (PPA).

MicroEvo uses Monte Carlo Tree Search to manage exploration, while the LLM generates candidates. It first creates valid combinations biased toward maximum performance, maximum efficiency, or a balanced objective, then applies two evolutionary operations: the knowledge tuner adjusts interdependent parameters near strong parent nodes, while the pattern explorer compares sibling nodes and attempts larger architectural pattern changes. Model outputs outside the design space are mapped to the nearest valid values, while actual CPI, power, and area are still evaluated with gem5 and McPAT; the LLM is not used to predict PPA.

The search strategy also differs from conventional UCT with a single reward. Pareto-UCT simultaneously considers a candidate’s marginal contribution to hypervolume, crowding distance in the objective space, and an exploration term; the exploration weight gradually declines as the budget is consumed. The system also converts successful design differences between parent and child nodes into reusable rules, retrieves them according to their historical hypervolume contributions and usage counts, and uses a finite-state controller to switch among exploit, balance, and explore prompting modes, preventing the search from remaining trapped in the same local region.

The authors completed 45 simulations using five initial points and 10 expansion rounds, averaging the results across five independent trials. In the primary configuration, the Gemini-3-pro version improved hypervolume by up to 36.22% over NSGA-II. To reach an HV of 0.74, it required 10.6 times fewer evaluations than NSGA-II. In searches using DeepSeek-V3.2, LLM inference accounted for only 7.31% of total execution time, with hardware simulation remaining the dominant cost. The MIT-licensed code has been released publicly, including xs-gem5 and McPAT interfaces and output tracking. However, the results are still based on simulators and analytical models rather than silicon measurements, and it remains to be verified whether the gains persist across different models, prompts, and simulator versions.