AI 晶片與推論
Extropic Z1T Rewrites the Transformer for a Probabilistic Chip, but Its 100× Energy-Savings Claim Still Excludes Key Costs
Z1T maps part of the decoding workload onto Extropic’s Z1 probabilistic-bit chip using fixed four-way sparse projections, Dynamic Tanh, and convolutional attention. The code and one set of weights are public, but the energy-efficiency and throughput figures come primarily from hardware models rather than complete end-to-end measurements.
Extropic has unveiled Z1T, an attempt to design a model architecture around the fixed sparse topology of its Z1 probabilistic chip instead of porting an existing dense Transformer unchanged to new hardware. Each Z1 chip contains 269,568 probabilistic bits (pbits), with only 16 hardwired couplings per node. Z1T therefore restricts each projection output to four inputs and uses four pbits to represent an approximate low-precision value. Repeated samples can then be averaged, trading more samples for higher effective precision.
The architecture also replaces several GPU-oriented components: RMSNorm gives way to Dynamic Tanh, which can be mapped to a sampling circuit, while softmax self-attention is replaced by gated convolutional attention with local convolution and cumulative pooling. Sparse tanh-linear layers run on Z1, while residual connections, pooling, positional processing, and other dense operations remain on an FPGA, forming a heterogeneous pipeline. The public JAX repository includes the sparse model and the Z1T training recipe, while Hugging Face hosts the first Z1T-0 weights, allowing researchers to inspect the architecture and loss curves on conventional hardware.
According to the company’s estimates, a four-layer test model with a width of 512 consumes about 294.52 nJ per token when the final vocabulary-logit layer and inter-chip data movement are excluded. Assuming an H100 achieves only 10% of its theoretical utilization, that implies a roughly 139× advantage. However, the FPGA already accounts for more than 95% of the estimated energy consumption. Adding the final vocabulary readout on the FPGA raises the estimate to about 136.4 µJ, and the number of Z1 chips required to operate in parallel has not been modeled. The stated throughput of 17,000 tokens/s likewise comes from a latency model rather than a complete system measurement. The real question is not whether this will “replace GPUs,” but whether the team can publish end-to-end measurements of power, I/O, batching, quality, and total silicon area on a physical multi-chip board—and demonstrate that the gains from hardware–model co-design survive the system costs currently left out of the estimate.