AI 基礎設施
Cerebras CS-4 Combines Three WSE-3T Chips in a Rack-Scale System, Boosting Peak Bandwidth to 129.6 PB/s
Rather than moving to a new process node, the CS-4 increases the WSE-3’s clock speed, power delivery, and I/O, then combines three wafer-scale processors in a Nexus rack. Cerebras claims inference speeds of up to 30 times those of GPU-based systems, but its PFLOPS and throughput-per-watt figures still lack comparable independent end-to-end testing.
Cerebras has unveiled the CS-4, integrating three WSE-3 Turbo (WSE-3T) processors into its new Nexus rack-scale architecture. The complete system is rated at 750 PFLOPS of AI compute, 129.6 PB/s of memory bandwidth, 160.5 PB/s of on-chip interconnect bandwidth, and 7.2 Tb/s of external I/O. Inter-wafer latency has been reduced from 5 microseconds on the CS-3 to as low as 2 microseconds. The first systems are scheduled to ship this quarter.
Notably, the WSE-3T is not built on a new process node. It retains the WSE-3’s 5 nm design, 4 trillion transistors, 900,000 cores, and 44 GB of SRAM per wafer. By moving power conversion closer to the processor, providing roughly twice the power-delivery capacity, and raising operating frequencies, Cerebras has increased the rated compute performance of each wafer from 125 to 250 PFLOPS. Three replaceable “Backpack” modules separate compute, power delivery, and I/O, improving deployment and serviceability.
For communications, the Wafer I/O Module supports both RoCE v2 RDMA and switchless Direct Wafer Links. The latter connects wafers across racks in a two-dimensional ring topology, aiming to enable low-latency pipeline parallelism for extremely large models. Cerebras is also positioning the system as the decode side of disaggregated inference: AWS Trainium or AMD Instinct can handle the compute-intensive prefill stage, then pass the state to the high-bandwidth SRAM for token-by-token decoding.
Engineering teams should not treat 750 PFLOPS as directly equivalent to GPU compute performance. The peak figure assumes sparse computation, and sparse acceleration may not apply to every LLM. The company’s claims of “up to 30×” performance and “10× higher throughput per watt” also combine internal and third-party comparisons. Key metrics to watch include actual power consumption, per-user latency under concurrent batching, the overhead of transferring state between prefill and decode, and how the rack’s 132 GB of SRAM constrains capacity for different model precisions and KV caches.