AI 硬體設計
ArchAgent v2 Evolves a Three-Level Prefetcher, Slightly Outperforming the Human Champion in DPC4 Simulation
ArchAgent v2 evolves L1D, L2, and LLC prefetchers in stages, using real-time capacity checks to eliminate candidates that exceed the hardware budget. The final design outperformed human champion BertiGO by 0.3% in the DPC4 simulation environment, but has not yet been validated on physical silicon.
Researchers from Google, Google DeepMind, and the University of California, Berkeley introduced ArchAgent v2, extending LLM-driven program evolution to prefetchers across three cache levels. Searching L1D, L2, and LLC simultaneously creates a non-monotonic combinatorial space: an improvement at one level may degrade another, while a single ChampSim evaluation can take more than 12 hours in the worst case. The new framework therefore evolves and freezes L1D first, then processes L2 and LLC in sequence, before finally enabling cross-level and multicore joint optimization.
Another key change is the inclusion of hardware feasibility in the feedback loop. Candidate programs must maintain `prefetcher_size()` in sync, while the compilation and simulation stages enforce state budgets of 32 KB for L1D, 128 KB for L2, and 256 KB for LLC. Designs that exceed these limits receive immediate negative feedback. The final design uses 31.1, 110.0, and 230.3 KB, respectively, and adds cross-page stride/delta tracking, an RL arbiter, and a throttling mechanism that adapts to memory bandwidth.
Under the same DPC4 rules and on held-out test traces, the authors report a 3.8% geometric-mean IPC improvement over the baseline, 0.3% higher than the human-designed champion BertiGO. In the low-bandwidth single-core configuration, the gain was 4.6%, compared with 2.6% for BertiGO. This demonstrates that agents can search for microarchitectural designs within strict simulator and capacity constraints, rather than merely generating high-level algorithms that cannot be implemented. However, the results still have clear limitations: the search took about two months, multicore gains were limited, capacity calculations ultimately required manual review, and ChampSim IPC and storage measurements cannot substitute for RTL, timing, area, power, and physical-process validation. The next questions are whether the generation strategy will be released and whether the gains can be reproduced across different trace datasets and synthesis flows.